An insulated-gate field-effect transistor (“IGFET”) is a semiconductor device in which a gate dielectric layer electrically insulates a channel zone of a semiconductor body from an overlying gate electrode. The channel zone extends between a source and a drain that adjoin a body region of the semiconductor body. The body region, often referred to as the substrate region or substrate, is of opposite conductivity type to the source and drain. Charge carriers, i.e., electrons for an n-channel IGFET and holes for a p-channel IGFET, move from the source through the channel zone to the drain when appropriate voltages are applied to the gate electrode, source, drain, and body region. By suitably controlling these voltages, the IGFET switches between on and off conditions.
The terms “normally off” and “normally on” are commonly used in describing an IGFET with regard to its conductive characteristics when the gate-to-source voltage is zero and the source is connected to the body region, i.e., the gate electrode, source, and body region are at the same voltage such as ground reference. In a normally off IGFET with zero gate-to-source voltage, substantially no charge carriers flow from the source to the drain when the drain is biased so as to attract charge carriers. Charge carriers flow from the source to the drain in a normally on IGFET at zero gate-to-source voltage with the drain biased to attract charge carriers.
The channel zone of an IGFET may be of the same conductivity type as, or of opposite conductivity type to, the source and drain. When the channel zone is of opposite conductivity type to the source and drain, the IGFET is usually a normally off device since no conduction path from the source to the drain extends through the channel zone at zero gate-to-source voltage. By applying a gate-to-source voltage suitable to place the IGFET in a conductive condition, charge carriers are attracted to the upper surface of the channel zone and cause inversion to occur in a thin surface layer of the channel zone. The inverted surface layer forms a conductive surface channel extending from the source to the drain. As a result, this type of IGFET is commonly referred to as a “surface-channel” device.
An IGFET that behaves generally in the way prescribed by the classical model for an IGFET is often characterized as a “long-channel” device. An IGFET is characterized as a “short-channel” device when the channel length is shortened to such an extent that the IGFET's behavior deviates significantly from that of the classical IGFET model. Both long-channel and short-channel IGFETs are variously employed in ICs. Long-channel IGFETs are particularly suitable for many types of analog circuitry. Short-channel IGFETs are prevalent in digital applications.
FIG. 1 illustrates a complementary-IGFET structure containing short-channel normally off n-channel surface-channel IGFET (“SCIGFET”) 20 and short-channel normally off p-channel SCIGFET 22 created from a doped monocrystalline silicon (“monosilicon”) semiconductor body as described in U.S. Pat. No. 6,548,842 B1. The “SC” portion of the acronym “SCIGFET” means surface channel rather than short channel. Field region 24 of electrically insulating material extends into the semiconductor body along its upper surface to define a group of laterally separated active semiconductor regions. Item 26 in FIG. 1 illustrates lightly doped p-type monosilicon material that remains after SCIGFETs 20 and 22 are created.
N-channel SCIGFET 20 has a pair of laterally separated n-type source/drain zones 30 provided in one of the active semiconductor regions along the upper semiconductor surface. Each n-type surface-adjoining source/drain zone 30 consists of very heavily doped main portion 30M and more lightly doped lateral extension 30E. Although more lightly doped than n++ main source/drain portions 30M, source/drain extensions 30E are still heavily doped n-type. P-type channel zone 32 extends between source/drain zones 30, primarily between n+ extensions 30E. Channel zone 32 is part of p-type device body material that forms a pn junction with each n-type source/drain zone 30. The p-type device body material consists of (a) well portion 34 that merges junctionlessly into p− material 26, (b) moderately doped upper portion 36, and (c) heavily doped halo region 38 that extends around source/drain extensions 30E to meet main source/drain portions 30M.
Gate dielectric layer 40 lies on channel zone 32. Gate electrode 42 consisting of very heavily doped n-type polycrystalline silicon (“polysilicon”) lies on gate dielectric layer 40 and extends laterally above part of each source/drain extension 30E. A pair of electrically insulating sidewall spacers 44 are situated respectively along the opposite transverse sidewalls of n++ gate electrode 42. A metal silicide layer 46 is situated along the top of each main source/drain portion 30M. Further metal silicide layer 48 is situated along the top of gate electrode 42.
Configured similarly to n-channel SCIGFET 20, p-channel SCIGFET 22 has a pair of laterally separated p-type source/drain zones 50 provided in another of the active semiconductor regions along the upper semiconductor surface. Each p-type surface-adjoining source/drain zone 50 consists of very heavily doped main portion 50M and more lightly doped, but still heavily doped, lateral extension 50E. N-type channel zone 52 extends between source/drain zones 50, primarily between p+ extensions 50E. Channel zone 52 is part of n-type device body material that forms a pn junction with each p-type source/drain zone 50. The n-type device body material consists of (a) heavily doped well portion 54 that adjoins p− material 26 to form a pn isolation junction, (b) moderately doped upper portion 56, and (c) heavily doped halo region 58 that extends around source/drain extensions 50E to meet main source/drain portions 50M.
Gate dielectric layer 60 lies on channel zone 52. Gate electrode 62 consisting of very heavily doped p-type polysilicon lies on gate dielectric layer 60 and extends laterally above part of each source/drain extension 50E. A pair of electrically insulating sidewalls spacers 64 are respectively situated along the opposite transverse sidewalls of p++ gate electrode 62. A metal silicide layer 66 is situated along the top of each main source/drain portion 50M. Further metal silicide layer 68 is situated along the top of gate electrode 62.
SCIGFETs 20 and 22 operate across the same voltage range. Their gate dielectric layers 40 and 60 are of largely the same (average) thickness. The magnitudes (absolute values) of their threshold voltages at a given channel length are also largely the same. In particular, the magnitudes of their threshold voltages are typically in the vicinity of 0.5 V for a scaled complementary-IGFET fabrication process using minimum lithography features of 0.18-0.25 μm.
IGFETs 20 and 22 are highly advantageous, especially for use in digital applications. The threshold voltage of a surface-channel IGFET rolls off sharply to zero as its channel length is reduced below a value typically in the vicinity of 0.4 μm. With one source/drain zone 30 or 50 operating as the source at (any particular time) while the other source/drain zone 30 or 50 operates as the drain, halo regions 38 and 58 cause threshold voltage roll-off to be shifted to lower channel length in IGFETs 20 and 22, thereby enabling their channel lengths to be reduced without significantly increasing the threshold voltage roll-off. Inasmuch as the source/drain drive current normally increases with decreasing channel length, the reduced channel length achieved with halo regions 38 and 58 enables IGFETs 20 and 22 to have increased drive current as is important for digital applications.
A pair of depletion regions (not shown) extend respectively along the drain/body and source/body junctions of an IGFET. Under certain conditions, especially when the channel length is small, the drain depletion region can extend laterally to the source depletion region and merge with it below the upper semiconductor surface. This phenomenon is termed punchthrough. If the drain depletion region punches through to the source depletion region, the operation of the IGFET cannot be controlled with the gate electrode. Accordingly, punchthrough normally needs to be avoided.
The net dopant concentration in the device body material, specifically upper portion 36 or 56, of each SCIGFET 20 or 22 reaches a local subsurface maximum more than 0.1 μm below the upper semiconductor surface but not more than 0.4 μm below the upper semiconductor surface. The local subsurface maximum of the net dopant concentration of the body material for IGFET 20 or 22 also occurs below a channel surface depletion region (not shown) that extends along the upper semiconductor surface into channel zone 32 or 52 during IGFET operation. The semiconductor dopant which produces the local subsurface maximum in the body material's net dopant concentration for IGFET 20 or 22 causes the thickness of the body-side portion of the depletion region along each source/drain zone 30 or 50 to be reduced at a given voltage between zones 30 or 50. Punchthrough is thus significantly alleviated in IGFETs 20 and 22 so as to significantly improve IGFET performance.
When the channel zone of an IGFET is of the same conductivity type as the source/drain zones, the channel zone is of opposite conductivity type to the body region and forms a channel-zone/body pn junction with the body region. An IGFET of this type can be a normally on device or a normally off device as described in Nishiuchi et al., “A Normally-off Type Buried-Channel MOSFET for VLSI Circuits”, IEDM Tech. Dig., December, 1978, pp. 26-29. Referring to U.S. Pat. No. 5,952,701, current conduction in such a normally off IGFET can occur along the upper surface of the channel zone or through a subsurface layer of the channel zone.
An IGFET having a channel zone of the same conductivity type as the source and drain is variously referred to by persons working in the semiconductor art using the following terms: “buried-channel MOSFET”, “implanted-channel MOSFET”, and “junction MOSFET”. Unfortunately, all of these terms are unsatisfactory. For example, characterizing such an IGFET as a “buried-channel MOSFET” is misdescriptive because source-to-drain conduction can occur through either a surface channel or a subsurface (buried) channel. As to “implanted-channel MOSFET”, the channel zone is normally created by ion implantation but does not have to be ion implanted. The term “junction MOSFET” does not make it clear that the “junction” is the channel-zone/body junction. Consequently, “junction MOSFET” is confusingly similar to the term “junction field-effect transistor” applied to a field-effect transistor having no gate dielectric layer.
Herein, an IGFET whose channel zone is of the same conductivity type as the source and drain is generally referred to as a “channel-junction insulated-gate field-effect transistor,” where the modifier “channel-junction” refers to the pn junction formed between the channel zone and the body region. Consequently, a channel-junction insulated-gate field-effect transistor (“CJIGFET”) generally means any transistor commonly referred to as a buried-channel MOSFET, an implanted-channel MOSFET, or a junction MOSFET. In particular, a normally off CJIGFET is a normally off IGFET having a channel zone of the same conductivity type as the source and drain.
CJIGFETs are often used in complementary-IGFET applications in which one of the two types of opposite-polarity IGFETs is a normally off CJIGFET while the other type is a surface-channel IGFET. In Hu et al., “Design and Fabrication of P-channel FET for 1-μm CMOS Technology,” IEDM Tech. Dig. 11-15 December 1982, pages 710-713, the p-channel device is a normally off CJIGFET while the n-channel device is an SCIGFET. The opposite occurs in Parrillo et al., “A Fine-Line CMOS Technology That Uses P+ Polysilicon/Silicide Gates for NMOS and PMOS Devices,” IEDM Tech, Die., December 1984, pages 418-422.
SCIGFETs and normally off CJIGFETs have various advantages and disadvantages. For instance, an SCIGFET is typically easier to fabricate, especially with a threshold voltage that stays within desired limits at short channel length. On the other hand, a normally off CJIGFET typically has lower noise. See Hu et al., cited above, and Nishida et al., “SoC CMOS Technology for NBTI/HCI Immune I/O and Analog Circuits Implementing Surface and Buried Channel Structures”, IEDM Tech. Die., 2-5 December 2001, pages. 39.4.1-39.4.4.
IGFETs, especially long-channel IGFETs, employed in analog circuitry commonly operate across greater voltage ranges than short-channel IGFETs utilized in digital circuitry. As a result, the thickness of the gate dielectric layer of an IGFET designed for analog circuitry is often greater than the thickness of the gate dielectric layer of an IGFET designed for digital circuitry. In mixed-signal applications having both digital and analog circuitry, semiconductor fabrication processes commonly provide complementary IGFETs at two different gate dielectric thicknesses so that complementary IGFETs at a low gate dielectric thickness are available for the digital circuitry while complementary IGFETs at a high gate dielectric thickness are available for the analog circuitry.
FIG. 2 generally depicts a complementary-IGFET structure having a first pair of normally off complementary IGFETs 80 and 82 at one gate dielectric thickness and a second pair of normally off complementary IGFETs 84 and 86 at another (different) gate dielectric thickness as described in Nishida et al. cited above. Recessed electrically insulating field region 88 laterally separates the source/drain zones of each IGFET 80, 82, 84, or 86 from the source/drain zones of each other IGFET 80, 82, 84, or 86. Various wells (not shown) are provided in semiconductor body 90.
IGFETs 80 and 82, which are at the higher gate dielectric thickness, operate across the higher of a pair of voltage ranges. IGFET 80 is an n-channel surface-channel device. IGFET 82 is a p-channel channel-junction device. Item 92 is the p-type channel zone for CJIGFET 82. Nishida et al. does not indicate that any special means is utilized to alleviate punchthrough in high-voltage IGFETs 80 and 82.
IGFETs 84 and 86, which are at the lower gate dielectric thickness, operate across the lower voltage range and are shown as being of lesser channel length than IGFETs 80 and 82. IGFET 84 is a n-channel surface-channel device. IGFET 86 is a p-channel surface-channel device. Low-voltage SCIGFETs 84 and 86 are similar to SCIGFETs 20 and 22 of FIG. 1 except that IGFETs 84 and 86 are not provided with halo regions to alleviate short-channel threshold-voltage roll-off. Nor does Nishida et al. indicate that any means is employed to alleviate punchthrough in low-voltage IGFETs 84 and 86.
Low-frequency noise that occurs in an IGFET is commonly referred to as “1/f” noise because the low-frequency noise is usually roughly proportional to the inverse of the IGFET's switching frequency. Nishida et al. reports that implementing p-channel high-voltage IGFET 82 as a channel-junction device improves the noise characteristics by causing the 1/f noise to be reduced to about one third of the 1/f noise that would occur if IGFET 82 were a surface-channel device. Unfortunately, n-channel high-voltage SCIGFET 80 appears to be relatively noisy. It would be desirable to have a semiconductor technology in which complementary IGFETs are provided at two different gate dielectric thicknesses such that the complementary IGFETs at the higher gate dielectric thickness incur less 1/f noise than high-voltage IGFETs 80 and 82.